HYBRID SEMINAR IN 13-2-005 AND ZOOM
The RD53C ATLAS and CMS chips are the final pixel readout chips for the phase 2 upgrades, designed for hit rates as high as 12 GHz per chip and developed in 65 nm CMOS technology. After several years of development and testing of pre-production chips, the RD53C-ATLAS is now in the production phase while the RD53C-CMS is currently in its final development stage. Designing a highly complex chip that operates reliably in an extremely hostile radiation environment, sustaining an inner layer Total-Ionising-Dose of 1 Grad and Single-Event-Upset (SEU) rate of 200 Hz per chip, was a major challenge.
This seminar will discuss a design approach for soft error mitigation in a chip with 15 million SEU-sensitive bits embedded in a complex architecture with time-tag-based latency buffering. Only ~15% of the design can use classical triple-modular-redundancy hardening techniques, constrained by area and power requirements. Problems identified in the pre-production chips during several proton and ion beam testing campaigns will be addressed. Two-Photon Absorption (TPA) laser testing and SEU verification were done to understand the root causes of the identified issues and to improve the robustness of the final chips to single-event-effects. The TPA laser-testing pinpointed an area sensitive to Single-Event-Transients (SETs) that was causing long link dropouts and enabled a detailed SET-sensitivity study of critical analog IPs. This seminar will show extensive SEE simulation results, introducing the fault simulation flow inside the RD53 Universal Verification Methodology framework. Identified SEU issues and corresponding design optimizations will be highlighted. We will conclude with a detailed SEE characterization of the final chip and verification-based estimates of its operation in the HL-LHC.
Zoom details are also in the invitation email.
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