The Timepix4 chip is a new hybrid pixel detector chip designed in the context of the Medipix4 collaboration1. The ASIC contains an array of 448x512 pixels compatible with an array of sensor pixels of 55 µmx55 µm for a total active area of ~7 cm2. By using TSV technology for the IO pads, on-chip pad to pixel redistribution and ‘hiding’ all active peripheral circuitry under the pixel bump pads we have designed a 4-side buttable chip with an effective active area > 99.5%. The chip has two main operation readout modes: 1) a zero-suppressed data-driven event-by-event readout mode, called TOA/TOT mode, and 2) a frame-based Continuous-Read/Write-Mode (CRW) with two 8b or 16b counters, called photon counting (PC) mode. In TOA/TOT mode each detected event sends a data packet of 64-bits which once decoded translates to pixel address (18-bit), timestamp (23-bit, LSB of 195ps), energy (15-bit, LSB of ~60-100 e-) and pileup (1-bit) at a maximum rate of 10.8 kHz/pixel. The chip integrates in each pixel column a Digital-DLL providing a robust PVT controlled time reference in order to achieve a full-chip 200ps time resolution. In PC mode the chip should sustain particle rates of up to 800 Ghits/cm2/s. The chip is currently in fabrication and in this talk we will present the chip, the design strategy and its expected performance.