The High Luminosity era of the LHC will pose unprecedented challenges for event reconstruction, with up to 200 proton–proton collisions per bunch crossing. To mitigate the resulting extreme pileup conditions, the CMS experiment is undergoing a major upgrade that includes the installation of the MIP Timing Detector (MTD). By providing precise time measurements for charged particles with a projected resolution of 30–60 ps, the MTD will enable 4D vertexing, significantly improving track-to-vertex association, object identification, and sensitivity to new physics signatures.

The MTD consists of two complementary subsystems: the Barrel Timing Layer (BTL) and the Endcap Timing Layer (ETL). In this context, two dedicated seminars will be presented, one focusing on the BTL and the other on the ETL.

The first seminar will be devoted to the BTL. The BTL will measure the time of arrival of charged particles in the CMS barrel region with 30–60 ps precision throughout HL-LHC operation. The detector is realized as a thin (<4 cm), large-area (>38 m²) system based on LYSO:Ce scintillating crystal bars read out by silicon photomultipliers (SiPMs) and a custom TOFHIR ASIC. A key challenge is the radiation-induced increase in SiPM dark current, which is addressed through a combination of ASIC-level mitigation and advanced thermal management, including dual-phase CO₂ cooling and Peltier elements that allow operation down to −45 °C and opportunistic annealing. The seminar will review the BTL design, performance validated in laboratory and beam tests, and the current construction status, with a large fraction of detector components already assembled, qualified, and delivered to CERN for final qualification prior to installation and commissioning in the CMS Tracker Integration Facility.

The second seminar will focus on the ETL, which provides precise timing for charged particles in the forward region (1.6 < η < 3) using low-gain avalanche diodes (LGADs) with a 50 µm active thickness. The sensors are read out by the ETROC ASIC, implemented in 65 nm CMOS technology. Each ETROC chip hosts a 16 × 16 pixel matrix with a pixel size of 1.3 mm × 1.3 mm and is bump-bonded to an LGAD sensor to form the basic ETL hybrid. The ETROC2 chip represents the first full-size, fully functional prototype and has undergone an extensive characterization campaign over the past three years, including operation in a mini-system environment with lpGBT and VTRX+ readout. These studies have validated the expected performance and demonstrated the full readout chain. The seminar will present an overview of the ETL design, key results from the characterization campaign, and the current project status, highlighting recent system-level achievements.